Senior Analog/Mixed Signal Design Engineer

Onsite | San Jose, California | Base salary up to $190,000, plus bonus and benefits This is an onsite opportunity for an experienced analog and mixed-signal IC design engineer who wants meaningful technical ownership in a collaborative semiconductor environment.

You will design and deliver advanced CMOS integrated circuits for next-generation automotive, surveillance, and imaging systems, working closely with analog, RTL, layout, verification, lab, customer, and partner teams from concept through production silicon.

The role is based in San Jose because hands-on collaboration is central to the work: design reviews, cross-functional problem solving, silicon bring-up, lab validation, and rapid iteration with the broader engineering organization. Candidates currently located outside the Bay Area who are prepared to independently relocate to San Jose for a long-term onsite role are encouraged to apply.

This is an opportunity to join a stable, technically rigorous team where engineers share knowledge, mentor one another, and contribute directly to high-performance products used in demanding real-world applications.

For engineers considering a move to the Bay Area, the role offers broad technical ownership, direct exposure to the full IC development lifecycle, regular collaboration with customers and partners, and a long-term platform to deepen expertise in high-performance video and imaging technologies.

Key Requirements

Eight or more years of hands-on analog or mixed-signal IC design experience supporting commercial silicon products built on advanced CMOS processes.

Proven experience delivering reliable, high-volume silicon products for performance-sensitive or demanding operating environments.

Strong proficiency with Cadence, Synopsys, or comparable EDA tools for schematic capture, circuit design, simulation, layout review, parasitic extraction, and verification.

Experience leading or contributing across the full IC development lifecycle, including requirements definition, architecture, simulation, tapeout, silicon bring-up, lab validation, characterization, debugging, and optimization.

Ability to partner effectively with digital RTL, physical-layout, verification, applications, lab, customer, and external-partner teams to deliver production-ready silicon.

Hands-on experience with silicon characterization, lab-data analysis, and design optimization for yield, power, noise, reliability, and manufacturability.

Clear technical documentation skills, along with the ability to lead technical reviews, mentor junior engineers, share knowledge, and communicate complex design tradeoffs to technical and business stakeholders.

Willingness to work onsite in San Jose, California, where close collaboration across analog design, layout, verification, lab validation, and silicon bring-up teams is central to the role.

Candidates outside the Bay Area should be prepared to independently relocate to San Jose for this long-term onsite opportunity.

What’s Next?

This is a full-time, onsite position based in San Jose, California. The base salary is up to $190,000, with additional bonus or incentive opportunity and a comprehensive benefits package.

Candidates currently in the Bay Area, as well as engineers prepared to independently relocate to San Jose for the right long-term opportunity, are encouraged to apply. To learn more, contact Hannah Duran at hannah.duran@robertwalters.com.